1. Field of the Invention
The present invention relates to information transmission. More specifically, the present invention relates to information transmission along conductive structures.
2. Background Information
Buses of parallel conductors are commonly used on circuit boards to carry data from one location to another. Problems associated with the use of such buses include delays incurred during propagation of the data signals and interference due to coupling of the conductors with one another.
Recently, it has become desirable to enable the use of buses of parallel conductors on small-scale structures such as within an integrated circuit (‘chip’). While the propagation delay may be minimal in such applications, undesirable coupling effects become more problematic. For example, capacitive coupling may occur between the parallel conductors, contributing to an increased impedance at high frequencies that limits bandwidth and distorts signal features. Such problems may impose undesirable limits on the maximum clock speed, the minimum size and separation of the conductors, and/or the maximum length of the bus in a particular application.
Timing considerations are especially critical in high-speed integrated circuits currently under development. In these circuits the time between state changes is minimal, and any fluctuation in the transition times may cause a delay that increases the error rate of the chip and decreases chip performance. In a chip clocked at 900 megahertz, for example, each cycle has a duration of only 1.1 nanosecond. If the time required to propagate a state transition across a transmission line is longer than a clock cycle, then the clock speed must be reduced.
As the conductors become more narrow and closer together, and as the time between state transitions decreases (e.g. as the clock speed increases), interference mechanisms that have negligible effects in other applications become limiting. In a 0.18-micron process, for example, with a pitch of 0.4 microns per wire, coupling effects may impede operation at any speed above a few hundred megahertz. For such reasons, chip designers commonly avoid long runs of parallel conductors in their designs.
One effect of coupling interference is an alteration of state transitions as they propagate over the conductors, resulting in a time skew of the signals being transmitted. When a new value is clocked onto a transmission line, an opposite current is induced in an adjacent (victim) transmission line. This induced current (or ‘crosstalk’) causes the skewing of a signal being transmitted on the victim line.
Timing within a circuit or assembly may be of critical importance: for example, when circuitry at the emitting and/or receiving sides of the transmission line is controlled by a clock (such as within an application-specific integrated circuit or ‘ASIC’). In such cases, an altered rise time of a state transition may result in a loss of synchronization between different parts of the circuit and the failure of the chip to perform properly. For example, a skew in rise time may cause a state change to be detected at the receiving side at a different time than was intended because the threshold voltage was reached before or after the intended time.
One method of reducing the effect of crosstalk among signals on parallel conductors includes increasing the power of the signal before transmission. As a result of recent advancements in integrated circuit technologies, however, this method has become outdated. Reduction in integrated circuit feature dimensions, for example, require a consequent reduction in the power supply voltages in order to maintain acceptably low electric field intensities.
An alternative approach to reducing the effect of crosstalk is to shield each transmission line individually in order to reduce the degree of crosstalk between adjacent lines. However, this method is also not viable for chip design because such shielding reduces the amount of surface area available on the chip for transmission lines and other circuit elements. A method of adding additional lines with balanced current and voltage values to counteract the effects of crosstalk and increase the distance between adjacent signal lines suffers from the same problem, as the additional lines will also consume surface area on the chip.
Repeaters have been used along transmission lines to decrease the total transmission time to a level at which the skew of the signal is acceptable. In other words, because delay may be due to both the skewing of the state transition and the propagation time, a reduction in the propagation time may reduce the total delay to an acceptable level. Again, however, such a method requires additional surface area on the chip (for the repeaters). Although methods exist to minimize the amount of space required for the repeaters, space limitations are still of major concern to chip designers. Additionally, the signals outputted by the repeaters may still interfere with signals on nearby conductors.
Reductions of scale and increased speeds associated with new integrated circuit designs require new and innovative techniques to reduce interference during information transmission.